Pavel Zichroni

Pavel Zichroni is a Senior Principal IC Design Engineer and Team Lead at Broadcom Inc., a position held since November 2006, where responsibility includes leading the design methodology for critical IPs and PON projects within the Broadband Video Group. Previous experience includes a role as a Senior VLSI Engineer at Tower Semiconductors from May 2004 to November 2006, focusing on circuit design adjustments, full design qualification, and automation of Memory Compiler flow. Earlier, as a Chip Designer at Analog Devices from December 2000 to May 2004, Pavel Zichroni handled micro-architecture and RTL design for digital blocks in TigerSHARC DSP processors. Educational background includes a B.Sc. in Electronic Engineering from Tel Aviv University, obtained between 1998 and 2002.