Avijit Dutta

Avijit Dutta, PhD, has extensive experience in optimization algorithms and design-related R&D within the semiconductor industry. Currently serving as an Architect at Cadence Design Systems since July 2018, Avijit previously held a Senior Staff position at Synopsys and worked as a Principal Engineer at Cypress Semiconductor, focusing on Programmable System-on-Chip (PSoC) and related verification processes. Earlier roles include Technical Lead at Mentor Graphics and a Member of Technical Staff at Cadence Design Systems, where contributions were made to verilog and VHDL simulators. Avijit Dutta earned a PhD and MS in Electrical and Computer Engineering from The University of Texas at Austin and holds a Bachelor's Degree in Computer Science from Jadavpur University. Additionally, Avijit completed a course in Machine Learning at Stanford University in early 2023.