Harshal Advane

Harshal Advane is a seasoned engineer with extensive experience in design verification and engineering roles across multiple esteemed companies. Currently serving as a Senior Principal Design Engineer at Cadence since November 2025, Harshal previously held the position of Senior Design Verification Engineer at Marvell Semiconductor from December 2018 to November 2025. Additional roles include MTS at Mirafra Technologies (April 2017 - December 2018), Senior Project Engineer at Wipro (August 2015 - April 2017), and MTS at Sibridge Technologies (January 2013 - August 2015). Earlier in the career, Harshal worked as an ASIC Verification Engineer at L&T Infotech, focusing on USB 3.0 xHCI_HOST verification, and as a Verification Engineer at Synopsys, initially managing VCS version verification and bug fixes. Career began at Accenture Services Pvt. Ltd. as an ASE. Educational qualifications include a Bachelor's Degree in Electrical, Electronics and Communications Engineering from Sinhgad College of Engineering and a BE in Electronics and Telecommunication from Savitribai Phule Pune University, both completed in 2008.