Kedar K.

Kedar K. is an experienced engineering professional with a strong background in physical design and technology leadership. Currently serving as a Senior Principal Design Engineer and Senior Manager at Cadence Design Systems since January 2014, Kedar K. specializes in complex DDR PHYs for advanced nodes. Previous roles include Senior Staff Physical Design Engineer at SanDisk and SMTS Engineer at AMD, working on high-speed and low-power designs. Earlier experience includes positions at Hynix, Conexant Systems, Analog Devices, Ample Communications, and Synopsys, focusing on physical implementation, IP and process technology, and synthesis. Kedar K. holds an educational background from Texas A&M University-Kingsville.