Mandi Das

Mandi Das is a Solutions Engineer at Cadence Design Systems, having joined the company in July 2024. Prior experience includes roles as a Design Engineer at Apex Semiconductor from July 2022 to July 2024 and a Graduate Research Assistant at the University of Virginia, where work focused on energy-efficient hardware design for a deep neural network accelerator in collaboration with IBM. Mandi also served as a Layout Design Engineer at Qualcomm and Altran, contributing to advanced technology projects including the QPTC project and SERDES designs. Initial experience included a position as a Layout Engineer at Silabtech, where involvement in a calibration block project for 28nm FDSOI technology occurred, and training as an Engineering Trainee at RV-VLSI. Mandi's academic background includes a Master's degree in Electrical and Electronics Engineering from the University of Virginia and a B.Tech in Electronics and Communication from the National Institute of Technology Silchar.