Ming Cheung

Ming Cheung is a highly experienced Senior Principal Engineer at Cadence Design Systems, with a career spanning over two decades in ASIC design and engineering. Since joining Cadence in October 2002, Ming has been integral in the development and testing of the Innovus place and route tool, focusing on advanced design flows for TSMC's 7, 10, and 16 nm processes, while also managing teams to successfully tape out multiple high-gate-count ASIC chips. Previously, in roles at Lucent Technologies/Agere and Seagate Technology, Ming demonstrated expertise in ASIC chip specifications, functional and timing problem resolution using Verilog simulations, and chip design for disk drive controllers. Ming’s foundational experience at IBM involved leading projects for high-end mainframe designs. Ming Cheung holds a Master’s Degree in Electrical Engineering from Syracuse University and a Bachelor’s Degree in Electrical Engineering from the University of Missouri-Rolla.