Rupal Katare is a highly skilled engineering professional with extensive experience in the semiconductor industry. As a Principal Design Engineer at Cadence Design Systems since May 2023, Rupal contributes advanced expertise in design methodologies. Previously held roles include Senior Lead Engineer and Senior Engineer at Qualcomm from January 2018 to May 2023, and Component Design Engineer at Intel Corporation from October 2013 to December 2017, where Rupal was integral to the ASIC Design Team and managed responsibilities for various GPU subsystems and networking chip projects. Rupal's academic background includes a Master's degree in VLSI Design from VIT University Vellore and a Bachelor of Engineering in Electronics and Communications Engineering from the Oriental Institute of Science and Technology. Notable technical proficiencies include the use of Synopsys Design Compiler, IC Compiler, and Cadence RTL Compiler.
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