Subrahmanya S

Subrahmanya S is an experienced Principal Design Engineer specializing in physical design, currently working at Cadence Design Systems since September 2022. Subrahmanya has held various roles in physical design at Intel Corporation, including Lead Physical Design Engineer from September 2018 to September 2022, where responsibilities included full chip design planning and block-level collateral generation. Prior experience includes a Senior Physical Design Engineer position at Sankalp Semiconductor, focusing on block and subsystem implementations, and previous roles at SmartPlay Technologies and Intel Corporation as a Technical Intern. Subrahmanya holds a Master of Technology in VLSI Design and Embedded Systems from PES University and a Bachelor of Engineering in Electronics and Communications Engineering from S B M Jain College of Engineering.