Sushrut B. Veerapur

Sushrut B. Veerapur is a seasoned professional in design engineering and technical management, currently serving as the Design Engineering Group Director at Cadence Design Systems since June 2015, where responsibilities include overseeing Controller IP, subsystem, and test chip verification groups for high-speed interface technologies. Prior experience includes roles at Emulex, AppliedMicro, LSI Corporation, CreativeDemons Inc., Freescale Semiconductor, and Sasken Communications, contributing to complex verification and design projects, developing UVM verification environments, and managing teams. Educational qualifications include a Master of Science in System Level Integration and SoC Design from The University of Edinburgh, a Mini-MBA in Performance Leadership from the University of California, Berkeley, and a Bachelor of Engineering in Electronics and Communications from Visvesvaraya Technological University.