Tim Low

Tim Low is an experienced architect at Cadence Design Systems, specializing in SPECTRE technology and overseeing worldwide engagements with Intel. With a career spanning over 25 years at Intel Corporation, Tim held multiple roles, including Sr Platform Architect and Technical Design Lead, where focus was on accelerating data center workloads and providing hardware solutions for low-latency FPGA interconnects. As an Analog Mixed Signal Technical Lead, Tim excelled in developing validation methodologies and modeling analog circuit components. Tim began as a Sr Design Engineer, concentrating on high-speed serial IO and analog mixed signal VLSI design. Tim holds a Master’s degree in Electrical Engineering from Oregon State University.