Cadence Design Systems
Tushar Malik is a Design Engineer specializing in Signal and Power Integrity at Cadence Design Systems, with experience since April 2014. In this role, Tushar Malik is responsible for creating IBIS files for DDR, LPDDR, and GDDR PHYs, as well as building system-level testbenches to test signal and power integrity using Virtuoso and Sigrity/Allegro tools. Prior to this position, Tushar Malik interned at DKOP Labs Pvt. Ltd. from 2013 to 2014 and holds a Bachelor of Technology (B.Tech.) degree in Electronics and Communications Engineering from ITM University Gurgaon, obtained in 2013.
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