Vaibhav Patil

Vaibhav Patil is a Design Engineer I at Cadence Design Systems, starting in January 2024, following a role as an Embedded Engineer at Virtuoso Projects & Engineers Pvt Ltd from August 2023 to December 2023, where OCPP protocol implementation using Websockets and STM32 architecture was carried out. Previously, Vaibhav served as a Design Engineering Intern at Cadence Design Systems from August 2022 to July 2023, focusing on digital signal processing by analyzing reference C code and optimizing kernels for the HiFi1 core. Vaibhav also gained experience as an intern at Wipro from February 2022 to April 2022. An academic background includes a Bachelor of Technology in Electronics Engineering from Walchand College of Engineering, completed in June 2022, along with HSC in Science from Ligade Patil Junior College of Science and SSC from Shri Parvati Khemchand Vidyamandir.