Vimarsh Srivastava

Vimarsh Srivastava currently serves as a Principal Design Engineer at Cadence, a position held since September 2025. Prior experience includes over a decade at Arm, where Vimarsh advanced through roles from Graduate Engineer to Staff Design Engineer, focusing on SRAM/Register File architectures and the correlation of timing and power metrics across various foundries, with expertise in advanced technology nodes such as 55nm, 40nm, and 28nm. Vimarsh's earlier internships included a role at CSIR-National Physical Laboratory, developing thin film solar cells, and a trainee position at Hindalco Industries Limited, where knowledge of power plant processes was gained. Vimarsh holds an Engineer's Degree with MSc(Hons) in Physics and BE(Hons) in Electrical & Electronics from Birla Institute of Technology and Science, Pilani, completed in 2015.