CEA
Lorenzo Ciampolini is an accomplished embedded RISC-V system architect at CEA since July 2017, focusing on building a TLM model for RISC-V ASICs and previously contributing to memory design and advanced technology projects. Prior experience includes a senior design engineer role at STMicroelectronics from 2008 to 2017, where contributions were made to SRAM design and technology benchmarking through numerical simulations. Earlier roles at STMicroelectronics involved TCAD engineering, focusing on semiconductor processing simulations, and a freelance researcher position at Institut Laue Langevin, optimizing instrument performance. Lorenzo's academic background includes a Ph.D. in Microelectronics from ETH Zürich and a Laurea in Solid State Physics from Università degli Studi di Firenze.
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