JK

Jyothsna Sree K

Design Verification Engineer at Celestial AI

Jyothsna Sree K has a diverse work experience in the field of design verification engineering. Jyothsna Sree began their career as a VLSI DFT Project Engineer at Wipro Technologies, where they gained hands-on experience in Design for Testability (DFT) and worked on FullScan and Compression ATPG simulations. Jyothsna Sree also honed their skills in debugging and analyzing timing violations.

Jyothsna then joined Intel Corporation as a Graduate Technical Intern, where they worked on timing simulations, debugging timing violations, and analyzing timing constraints using PrimeTime tool. Jyothsna Sree also gained a basic understanding of Tcl scripting during this time.

Continuing their journey at Intel Corporation, they became an IP Design Verification intern. Their responsibilities included working on the functional verification of a voltage regulator IP. Jyothsna Sree gained expertise in debugging checkers using Verdi, analyzing sequences, and working with the testbench environment. Jyothsna Sree also gained knowledge in OVM (Open Verification Methodology) and UPF (Unified Power Format).

Jyothsna further expanded their expertise by joining Xilinx as a Design Verification Engineer. Here, they developed test plans for performance verification, focusing on latency and bandwidth requirements for the Network on Chip (NoC) and High Bandwidth Memory. Jyothsna Sree automated and optimized the verification simulation setup using Python and Perl. Jyothsna Sree also conducted simulation result extractions and compared them with theoretical calculations.

Most recently, Jyothsna joined Celestial AI as a Design Verification Engineer in 2022.

Jyothsna Sree K holds a Master's degree in Electrical and Computer Engineering, which was obtained from Portland State University. Jyothsna Sree attended Portland State University from 2017 to 2019. Prior to that, they completed their Bachelor of Engineering (B.E.) in Electronics and Communication Engineering at Osmania University, where they studied from 2010 to 2014. Their earlier education consists of completing high school at Sri Chaitanya College of Education, specializing in Mathematics, Physics, and Chemistry, from 2008 to 2010.

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Timeline

  • Design Verification Engineer

    September 1, 2022 - present