Jagadeesh Meesala

Jagadeesh Meesala is a Physical Design & Verification Engineer at Cerium Systems, a position held since March 2021. Prior to this role, Jagadeesh was a Physical Design Trainee at RV-VLSI VLSI and Embedded Systems Design Center from November 2019 to December 2020. Jagadeesh holds a Bachelor of Technology (BTech) degree in Electronics and Communication Engineering from Raghu Institute of Technology, completed in 2019.