Cerium Systems
Nirav Jain is a Silicon Design Engineer 2 at AMD since June 2024, with prior experience as a Formal Verification Engineer at Cerium Systems from August 2021 to June 2024, focusing on formal test plan creation and verification using SystemVerilog assertions and JasperGold software. In early 2021, Nirav completed a research internship at IIT Patna, where the work involved FPGA implementation of the CAN protocol and an exploration of its security aspects through Physical Unclonable Functions. Nirav holds a Bachelor of Engineering degree in Electronics engineering from Shri Ramdeobaba College of Engineering and Management, completed in 2021.
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