Cj Sandoval

CJ Sandoval is a Senior Digital Design Verification Engineer at Cirrus Logic, a position held since October 2022. Prior to this role, CJ worked at Intel Corporation from May 2017 to October 2022, serving as a Silicon Performance RTL Engineer and a System Validation Engineer, including a graduate internship in the same field. Earlier experience includes a Research Assistant position at the ASU Lab of Molecular Sciences from August 2016 to May 2017, as well as a Pre-Silicon Validation Internship at Intel Corporation's Atom Products Division from June 2013 to January 2014. CJ holds a Master of Science in Electrical and Computer Engineering and a Bachelor of Science in Electrical Engineering, both from the Ira A. Fulton Schools of Engineering at Arizona State University.