Gaurav Sharma

Gaurav Sharma is a highly experienced Sr. Mixed Signal Layout Design Engineer at Cirrus Logic, specializing in 22nm process technology for mixed analog circuit layouts used in Apple products since December 2019. Prior to this role, Gaurav worked as a Senior Layout Engineer at Ciena, contributing to the tapeout of the HYDRA testchip with 7nm ASIC layout designs. Gaurav's earlier career includes positions as a Sr. Layout Design Engineer at Sidense, Layout Designer at Global Foundries focused on 14nm finFET layout design for SERDES, and Physical Design Engineer at Intel, working on both 14nm and 28nm SERDES and RF physical design activities. Gaurav began the professional journey in design engineering at ST Microelectronics, focusing on SRAM memory design. Gaurav holds an M.Tech. in Microelectronics from Panjab University.