Steven Atherton

Steven Atherton is an accomplished IC Package Co-Design Engineer at Cirrus Logic since November 2015, leading a package design team focused on driving innovation and training junior engineers. His responsibilities include wafer level, flip chip, and wire bond package design, alongside electrical simulation. Previously, Steven held the position of Manager of Package Design, Reliability, and Simulation, overseeing a talented team across various areas. Prior experience includes ten years at Freescale Semiconductor as an IC Package Design Engineer, where Steven led co-design efforts to automate communication among global design teams, and five years at Motorola Semiconductor as a Hardware Design Engineer, where Steven developed design rules for Ball Grid Array packages. Steven holds a BA in Mechanical Engineering from The University of Texas at Austin, earned in 1999.