Rajesh Bawankule

Rajesh Bawankule is an experienced ASIC Design Engineer with a robust background in SoC architecture and integration, currently serving at Cisco since April 2025. Prior positions include Senior Principal ASIC Design Engineer at Palo Alto Networks and Staff SOC Design Engineer at Cruise. Rajesh has also held key roles at Cray Inc., Cavium Inc., Broadcom, Nokia, Zenverge, and FreeWire Technologies, contributing to the design and development of various ASICs and systems-on-chip. Educational qualifications include a Master of Technology in Electronic Design and Technology from the Indian Institute of Science and a Bachelor's degree in Electronics from Visvesvaraya National Institute of Technology.