Razeen Raoof is a Physical Design Engineer with extensive experience in various advanced technologies, including 3nm to 14nm. They served as a Senior Physical Design Engineer at Qualcomm from 2019 to 2021 and as a Physical Design Engineer at Cientra from 2016 to 2019. Currently, Razeen holds the position of ASIC Engineering Technical Leader at Cisco, and has recently worked as an ASIC Backend Engineer at Veriest. Razeen earned a Master’s degree in VLSI from Nehru College of Engineering and Research Centre and a Bachelor’s degree in Electrical, Electronics and Communications Engineering from RVS CET.
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