Birjender Singh is the Vice President at Citibank Europe Plc, a position held since 2020. Prior to this role, Birjender was a Bigdata Architect at Virtusa from 2015 to 2020 and served as a Project Manager at HCL Technologies Ltd. from 2004 to 2015. Earlier in their career, Birjender worked as a Technical Lead Architect at Netlink Digital Energy Pvt. Ltd. from 2001 to 2004 and began as a Software Developer at PG Softech Ltd, India in 2000. Birjender earned a Bachelor of Science (B.Sc.) degree from Meerut College, Meerut, after attending Dayawati Modi Academy in Modipuram from 1985 to 1992.
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