Antonis Psathakis

Antonis Psathakis has a diverse range of work experience in various engineering roles. Antonis started their career at ICS-FORTH in 2012 as a Graduate Research Assistant, where they worked on hands-on Network-On-Chip (NoC) design and ASIC flow. This included tasks such as RTL development, synthesis, STA, ATPG, and post-PnR simulation. Antonis also gained experience in energy evaluation and model generation for NoCs and memories.

In 2013, Antonis transitioned to the role of FPGA/RTL Engineer at ICS-FORTH, where they continued to work on FPGA SoCs, including small ARM CPUs and various peripheral blocks. Antonis also developed and modified RTL blocks such as AXI4 multi-channel packet initiators and FIFOs.

In 2016, Antonis joined Kaleao Ltd as an FPGA/RTL Engineer. Here, they were involved in the design and integration of IPs for complex FPGA SoC chips. Antonis worked on an in-house designed board called KMAX, which hosted multiple ARM CPUs, DRAM, high-speed networks, and NVMe SSDs.

Most recently, Antonis joined Codasip in 2023 as a Verification Engineer, where their responsibilities include developing and maintaining a cache controller for the European RISC-V Accelerator Processor. Antonis is involved in both RTL development and verification tasks, such as traffic injection, micro and macro architecture assertions, and testplan development.

Overall, Antonis Psathakis has extensive experience in RTL development, FPGA SoCs, NoC design, and ASIC flow. Antonis has a strong track record of successfully completing projects and contributing to various aspects of engineering development.

Antonis Psathakis completed their Bachelor of Applied Science (BASc) in Computer Systems Engineering at the Technological Education Institute of Piraeus from 2004 to 2009. Antonis later pursued further education and obtained an MSc in Computer Science with a specialization in Microelectronic Systems Architecture from the University of Crete, where they studied from 2010 to 2013.