Michael A Janinek

Michael A Janinek has held various engineering roles since 1985. Michael A began their career as an Engineer at the Naval Air Development/Warfare Center and then moved on to become a Senior Hardware Design Engineer at Max Control Systems in 1994. In 2000, they became a Principal Hardware Engineer at ARRIS and Motorola, where they made major contributions to the design, development, test, and deployment of Cable Infrastructure Products. From 2016 to 2019, they worked as a Hardware Design Engineer at Intel Corporation, where they were responsible for high speed digital design and integration of custom ASICs for high speed SerDes interconnects. Michael A is currently a Senior Hardware Design Engineer at Cornelis Networks, where they work on Printed Circuit Boards to bring High Performance Compute Networks to fruition.

Michael A Janinek completed their Bachelor of Science in Electrical and Electronics Engineering from Penn State University between 1981 and 1985. Michael A then went on to pursue their Master of Engineering in Computer Design from Penn State University, which they completed between 1987 and 1991.