William Vick

William Vick is a seasoned engineering professional specializing in ASIC verification with extensive experience in design verification roles across multiple companies. Currently serving as a Senior Design Verification Engineer at Cornelis Networks since June 2023, William has previously held similar positions at Luminous Computing and AMD, focusing on test planning, feature extraction, and development of sophisticated testbenches utilizing System Verilog and UVM methodologies. William’s career includes significant contributions at D. E. Shaw Research, ASML, L-3 Cincinnati Electronics, and Lockheed Martin Coherent Technologies, where expertise in large ASIC and FPGA verification was demonstrated through contract roles and integration efforts. William's background spans over a decade, with a thorough understanding of advanced verification techniques and tools.