gianpiero tartabini

Gianpiero Tartabini has been working in the FPGA engineering field since 2004. gianpiero began their career at Selex ES, where they were a VHDL designer working on an Avionic board. In 2006, they moved to ST-Ericsson, where they were a VHDL designer in the ASIC team. After that, they worked at Akronos Technologies as a VHDL designer in 2010, and then at Balance System S.r.l. as a VHDL designer and HW designer in 2008. In 2013, they moved to ML as a HW/VHDL designer and project manager, and then to Altran Italia S.p.A. as a VHDL designer and FW designer in 2014. In 2018, they began working as a self-employed FPGA designer and Self Employee IT for Free Lance. Most recently, they have been working as an FPGA Engineer at Cron AI since 2021.

Gianpiero Tartabini holds a Bachelor of Engineering (B.E.) degree from the Politecnico di Milano in Ingegneria elettrica, elettronica e delle comunicazioni.