Yossi Shanava

Yossi Shanava has extensive work experience in the field of engineering. Yossi is currently working as a Principal Design Engineer at DeepRoute.ai since November 2022. Prior to that, they held the position of Sr. Principal Engineer at Palo Alto Networks from May 2021 to October 2022.

Yossi has also worked at Marvell Semiconductor as a Senior Staff Engineer from February 2010 to May 2021. In this role, they were responsible for various tasks such as baseband phy 5G eCPRI compression decompression, data caching, and working on multi 3G blocks for base station chip. Additionally, they contributed to the development of HNA - Hyper Non-deterministic Automata.

Before their tenure at Marvell Semiconductor, Yossi was a Staff Design Engineer at AMCC from September 2006 to February 2009. Yossi played a crucial role in the design and implementation of the Traffic Manager subsystem in a highly integrated SoC. This subsystem supported up to 64K virtual queues (VQ) and provided hierarchical traffic base scheduling.

Yossi also worked at Broadcom as a Senior Staff Design Engineer in 2006. Here, they supervised the development of a current SoC mix signal chip and developed scripts for automating the bring-up process. Yossi also designed an emulation board to verify communication channels at a system level.

Furthermore, Yossi started their career as an ASIC Design Engineer at powerdsine in December 2003. Yossi then joined AMCC in May 2000 as an ASIC Design Engineer, contributing to the development of network processors for ATM and Ethernet up to 10Gb. Their responsibilities included specification definition, RTL coding, verification, synthesis, and static time analysis of various blocks.

Yossi Shanava completed a Bachelor of Science degree in Electrical Engineering from Technion - Israel Institute of Technology from 1995 to 1999.