Pavithra K

Pavithra K is a skilled Printed Circuit Board Design Engineer with extensive experience in layout design, EMC analysis, placement and routing, debugging errors, and Gerber generation. Currently employed at Dynamic Test Solutions Asia since March 2022, Pavithra previously held the same position at Valeo from July 2019 to August 2020. Prior to that, a role as a Design Engineer at Caliber Interconnect Solutions Private Limited spanned from September 2015 to July 2019, where responsibilities included creating schematics, managing layout libraries, and performing signal integrity analysis. Pavithra holds a Bachelor of Engineering in Electrical, Electronics and Communications Engineering from Sri Ramakrishna Engineering College, completed in 2014.