Hup Chin Teh

Hup Chin Teh has a diverse work experience in the field of engineering. Hup Chin started their career at SONY EMCS (Malaysia) Sdn Bhd in 2003, where they worked as a Product Engineer, specializing in new product introduction and technical support for the Sony Audio Biz Sector. In 2004, they joined Altera as a Product Engineer, where they handled volume manufacturing, yield improvement, and failure analysis for Altera Flex EPF10k & EPC devices. Hup Chin also led the rollout of various FPGA devices and played a key role in the migration of tester platforms. From 2014 to 2018, Hup Chin worked at Intel PSG / Altera as a Design Verification Engineer, primarily focusing on the design verification of various IP blocks in FPGA design. Hup Chin contributed to the development of UVM testbench methodologies and environments and promoted code reusability and automation. In 2018, they were promoted to the role of Design Engineering Manager at Intel Corporation, where they managed a front-end design team for the development of the next generation of Advanced Interface Bus subsystems. Hup Chin also led the delivery of the UIB subsystem for Intel Agilex product. Currently, Hup Chin Teh is working as a Principal Engineer at Efinix, Inc., starting in October 2022.

Hup Chin Teh attended Universiti Teknologi Malaysia from 1999 to 2003, where they pursued a Bachelor of Science degree in Industrial Physics.