Alexandre Falanga

Alexandre Falanga has a diverse work experience in the field of electronic engineering. Currently, they work as a VHDL designer for Elsys Design, where they are involved in building a secret ASIC for automotive applications. Prior to this, they worked at ThePhasedArrayCompany as an electronic engineer, focusing on improving communication protocols on FPGA for higher data rates. Alexandre also gained experience at Zodiac Data Systems, where they developed a serial division algorithm for FPGA. In addition, they worked at Siemens, where they created a computer tool using VBA to extract and decode data from text files.

Alexandre Falanga completed their degree in Electrical and Electronics Engineering from CentraleSupélec between 2012 and 2015. Prior to that, they attended Blaise Pascal college in France, although specific dates and degree information are not available.