Russell Kane

Russell Kane is an experienced ASIC Timing Lead and Timing Analysis Consultant with a robust background in semiconductor and EDA industries. Currently at Avera Semiconductor, Russell specializes in TSMC 7nm SerDes designs for automotive and 5G applications, with significant involvement in timing closure and optimization using Cadence tools. Previously, Russell has held roles at Qualcomm, Avago Technologies, and Cadence Design Systems, demonstrating expertise in timing analysis, synthesis, and formal checks. Russell has contributed to multiple startups and led significant projects leading to innovations in low-power designs. Educational achievements include a Bachelor's degree in Digital Circuits and Systems from the University of California, Davis, along with extensive professional development in engineering and management.