Gurjeet Singh

Gurjeet Singh is a seasoned professional in the field of ASIC design and microarchitecture, currently serving as MTS, MicroArchitect at Enfabrica since September 2020. Prior to this role, Gurjeet was a Member of Technical Staff at Fungible, Inc. from January 2018 to September 2020 and held multiple positions at Juniper Networks from 2012 to 2017, including Sr. Manager ASIC, focusing on multi-terabit network fabric chip architectures and performance modeling. Additional experience includes roles as Technical Leader at Cisco Systems India, where Gurjeet oversaw ASIC design and verification, and as Sr. Member Technical Staff at Intel, specializing in enterprise switching ASIC designs. Early career experience includes a Research Engineer position at the Centre For Development Of Telematics and an Engineer Trainee role at Bharat Electronics Limited. Gurjeet Singh holds a B. Tech in Electronics & Telecommunications from the National Institute of Technology Kurukshetra, earned between 1993 and 1997.