Xiangyu Liu

Xiangyu Liu began their work experience in 2019 as a Development Engineer at the University of California, Los Angeles. In this role, they worked from August 2019 to November 2019.

They then moved on to work at Western Digital as an Electronic Design Engineer from December 2019 to January 2023. In this role, they were responsible for high-speed datapath design for 1Tb QLC 3D NAND. Their tasks included designing data and clock repeater floorplans, optimizing repeater circuits to reduce data-clock skew, and building circuit models to evaluate and improve key parameters.

Currently, Xiangyu Liu is an Analog Design Engineer at eTopus Technology, starting in February 2023. No end date is provided for this role.

Xiangyu Liu pursued a Bachelor of Science in Electrical Engineering from Rose-Hulman Institute of Technology from 2013 to 2017. Later, from 2017 to 2019, Xiangyu enrolled in the University of California, Los Angeles (UCLA) to complete a Master of Science in Electrical and Computer Engineering.