Mkhitar Ghazaryan

Mkhitar Ghazaryan has worked in the IC Layout Design field since 2013. From 2013 to 2019, they worked at Synopsys Inc. as an A&MS Layout Design Engineer and A&MS Layout Design Engineer 2. During this time, they designed 10GHz High-Speed SerDes top and sub blocks, logic cells for TSMC28, TSMC16, TSMC10, SAMSUNG14, SAMSUNG10, and GF14 STD libraries, and test chips for main logic cells in TSMC16 and GF14 nodes. Mkhitar was also responsible for generating excel sheets with necessary information about STD library cells. In 2019, they began working at Ferroelectric Memory Company as a Sr. IC Layout Design Engineer. In this role, they designed FeRAM test chips and SLM structures from scratch using GF22FDSOI technology with PDK addON. Mkhitar also managed and worked on the creation of a 32mb macro block and the test chip from scratch using GF28 FeFET technology. This macro had several planes, analog parts, and digital parts. Mkhitar also had experience debugging, modifying, and enhancing layout driven python code.

Mkhitar Ghazaryan obtained a Bachelor's degree in Cybernetics from the National Polytechnical University of Armenia between 2007 and 2011. Mkhitar then obtained a Master's degree in Microelectronic Circuits and Systems, VLSI Design from the same university between 2013 and 2015. In September 2020, they also obtained a certification in Innovus Block Implementation with Stylus Common UI v20.1 Exam from Cadence Design Systems.