Aavula Sreekanth

Aavula Sreekanth is an experienced Analog Layout Design Engineer at Gaafet Semiconductor Pvt Ltd since December 2021, previously serving as an Analog Design Engineer at Abico Technologies Private Limited from October 2019 to December 2021. Prior experience includes an internship as a trainee at Staple VLSI from October 2018 to July 2019. Aavula Sreekanth holds a Bachelor of Technology degree in Electrical and Electronics Engineering from RGMCET, completed in May 2018.