Dvir Rune Peleg

Dvir Rune Peleg has extensive work experience in the semiconductor industry, primarily as a design engineer. Dvir Rune started their career at Freescale in 1997 and held the position of Senior Design Engineer for over 10 years. In this role, they gained expertise in various aspects of semiconductor development, including system level verification, block design in Verilog, chip level power estimation, system level integration, and backend design. Dvir Rune also played a significant role in defining the Semiconductor Reuse Standard. Since 2008, Dvir has been working at GN Group, where they initially served as a Senior Digital IC Engineer before being promoted to Lead Digital IC Engineer in 2023.

Dvir Rune Peleg completed their M.Sc. in Bio Medical Electronics Engineering at Tel Aviv University in 2004. Prior to that, they obtained their B.Sc. in Electronics Engineering from Tel Aviv University in 1997. Additionally, in December 2020, they obtained the Certified Associate in Project Management (CAPM) from the Project Management Institute. There is no information available about their education at IASA.