Ashish Purani

Ashish Purani has extensive experience in VLSI design and engineering, having held various roles in notable companies since 2008. Starting as a student at DOEACC Centre, Calicut, Ashish implemented and verified RTL code for an ALU module of an 8-bit RISC processor. A position as an Engineering Trainee at STMicroelectronics involved conducting studies on FDSOI technology and creating a reference manual showcasing its advantages. From November 2015 to February 2021, Ashish served as a Staff Engineer at Provino Technologies, followed by a current role as a Silicon Engineer at Google. Previously, Ashish worked as a Senior Technical Associate at eiTRA, focusing on frontend VLSI design and digital design validation using Verilog and FPGAs. Academic achievements include a Master’s degree in VLSI Design from Nirma Institute of Technology and several other qualifications in electronics and communications.