Pavan Yeluri

Pavan Yeluri is a Design Verification Manager with over 18 years of hands-on experience in ASIC, FPGA, and SoC verification. Currently at Google, Pavan leads design verification efforts in the Silicon department. Previously, Pavan held positions at Intel Corporation as a Design Verification Lead/Manager, at NVIDIA as a Senior Design Verification Engineer, and at Xilinx as a Senior Design Engineer focused on design verification. Pavan began their career at Wipro, where they worked as a Module Lead in ASIC verification. Pavan earned a degree in Electrical, Electronics, and Communications Engineering from the Indian Institute of Technology, Delhi.