Rakesh Paladugula is a skilled engineer with a background in Physical Verification and ASIC design. Starting a career at Aricent as a Physical Verification Engineer from February 2020 to December 2020, Rakesh then advanced to Synapse Design Inc. as a Senior Physical Verification Engineer from May 2021 to May 2024. Currently, Rakesh serves as an ASIC Physical Verification and Convergence Engineer at Google since April 2024. Rakesh holds a Bachelor of Technology degree in Electrical, Electronics, and Communications Engineering from Jawaharlal Nehru Technological University, Kakinada, earned between 2014 and 2017.
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