Brankica Zlokolica

Brankica Zlokolica is a Senior Verification Engineer at HDL Design House since February 2022. Previously, Brankica worked as a Design Verification Engineer at ELSYS Eastern Europe from July 2008 to January 2022, specializing in IP verification. Brankica has experience in IP verification, defining verification plans and environments, reusable UVC coding, Register Abstract Layer, assertions, cover groups, scoreboard, sequences, test cases, debugging tests, functional and code coverage. Brankica also has experience as a Mixed Signal IC Layout Engineer, working on RF & mixed signal IC layout for Texas Instruments. Brankica holds a Master's degree in Electrical and Computer Engineering from University Kragujevac.