HDL Design House
Jelica Janic is an accomplished Verification Engineer currently employed at Capgemini since May 2024, with prior experience as a Junior Verification Engineer at HDL Design House from August 2020. Earlier in their career, Jelica served as a teacher at Programming and Art School Da Vinci Studio between March 2019 and August 2020 and completed student internships at the Faculty of Electronic Engineering, University of Niš, and HTEC Group in 2020 and 2018, respectively, focusing on PCB design. Jelica holds a Master's Degree from the University of Niš, obtained in 2020, and a Bachelor's Degree from the same institution, completed in 2019, both in the Faculty of Electronic Engineering.