Bart McDaniel

Bart McDaniel possesses extensive experience in layout engineering, specializing in RFIC and analog design. Since March 2019, Bart has served as Principal Layout Engineer at Intrinsix Corp., focusing on custom RFIC developments that include LNA and mixer design for 28GHz in 8HP SiGe BiCMOS technology. Prior to this role, Bart worked as a Layout Design Engineer at Freescale Semiconductor and Qualcomm, contributing to high-speed SERDES, PHY IP, and analog circuitry for voltage regulators and SOC processes. Bart's career began at Intel Corporation, where significant contributions were made to the design of clocking and I/O circuits for three generations of ATOMtm processors. Bart holds a Bachelor of Science and Master of Science in Electrical Engineering from The University of Kansas and has completed doctoral coursework at Arizona State University.