Sze Yin Lee

Sze Yin (SY) Lee is a Distinguished Engineer at Lattice Semiconductor, with a previous role as Principal Engineer at Intel Corporation from January 2016 to May 2022, where responsibilities included serving as the PCIe architect for Intel FPGA products and defining next generation PCIe solutions for transceiver and data center acceleration. Prior experience includes positions as Principal Engineer and Senior MTS Digital Design Engineer at Altera and Intel, respectively, and Staff Digital IC Design Engineer at Avago Technologies. Sze Yin holds multiple patents related to media recognition technologies and earned a Bachelor of Engineering degree from Universiti Teknologi Malaysia in 2002.