LUBIS EDA
Advaith Sreevalsan is a Formal Verification Engineer at LUBIS EDA since April 2022, previously serving as a Student Assistant and Intern. Advaith gained internship experience at Hindustan Aeronautics Limited in July 2014. Educational qualifications include a Master's degree in Electrical and Computer Science from RPTU Kaiserslautern-Landau, earned between April 2020 and April 2023, and a Bachelor of Engineering in Electronics and Communication from B. M. S. College of Engineering, completed from 2015 to 2019. Advaith completed high school at Sharjah Indian School from 2009 to 2018.
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LUBIS EDA
LUBIS EDA is helping customers to find simulation-resistant and corner-case bugs in high-risk silicon design or IP blocks. Our formal verification service enables you to: 1) Reach your silicon design verification goals faster 2) Uncover hard to find functional bugs in your design 3) Require less RTL simulation time 4) Stay within your budget and tape-out schedule 5) Avoid re-spins and improve designer productivity We functionally verify your RTL with formal techniques and iteratively communicate bugs we find. You get short feedback cycles, reduce your time spent on RTL verification and higher-quality designs. What makes us special? We work with an innovative formal verification methodology, resulting in an easy to use, high quality formal Verification IP. Instead of writing SVA properties by hand we established a property generation flow. During a verification service project, we build a propriatary model that enables us to generate VIP. The VIP can later be used in simulation and/or formal verification of your choice.