LUBIS EDA
Osama Ayoub is a formal verification engineer currently employed at LUBIS EDA since October 2022, with a background in SoC design and formal verification through project work as part of a master's degree. Previously, Osama worked as a scout at Stats Perform since October 2015, a research assistant at SmartFactory Kaiserslautern from February 2022 to March 2023, and an automation engineer at Volt Automation from February 2020 to August 2021. Additional experience includes a bachelor's thesis role at Siemens Healthineers in 2018 and participation in the Young Innovation Fellowship. Osama holds a master's degree in Embedded Systems from RPTU Kaiserslautern-Landau (2021-2023) and a bachelor's degree in Mechatronics Engineering from German Jordanian University (2014-2020), with additional studies at TH Aschaffenburg University and The University of Freiburg.
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LUBIS EDA
LUBIS EDA is helping customers to find simulation-resistant and corner-case bugs in high-risk silicon design or IP blocks. Our formal verification service enables you to: 1) Reach your silicon design verification goals faster 2) Uncover hard to find functional bugs in your design 3) Require less RTL simulation time 4) Stay within your budget and tape-out schedule 5) Avoid re-spins and improve designer productivity We functionally verify your RTL with formal techniques and iteratively communicate bugs we find. You get short feedback cycles, reduce your time spent on RTL verification and higher-quality designs. What makes us special? We work with an innovative formal verification methodology, resulting in an easy to use, high quality formal Verification IP. Instead of writing SVA properties by hand we established a property generation flow. During a verification service project, we build a propriatary model that enables us to generate VIP. The VIP can later be used in simulation and/or formal verification of your choice.