LUBIS EDA
Rohith Babu Batthineni is a skilled engineer currently serving as a Formal Verification Engineer at LUBIS EDA since May 2023, where responsibilities include developing verification plans and creating high-level models for client designs. Prior experience at LUBIS EDA includes a role as a Working Student focused on a master's thesis project that enhanced existing verification tools. Rohith also contributed as a Student Research Assistant at the University of Kaiserslautern, developing customized DFI4.0 for LPDDR4 memory controllers, and served as a Student Assistant in embedded systems tutoring. Previous positions include Assistant Manager at Vedanta Limited, where projects involved automation and industrial digitalization in a thermal power plant, and various internships in embedded systems and electronic projects. Rohith holds a Master of Science degree in Embedded Computing Systems from RPTU Kaiserslautern-Landau and a Bachelor of Technology degree in Electronics and Communication Engineering from the National Institute of Technology Arunachal Pradesh.
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LUBIS EDA
LUBIS EDA is helping customers to find simulation-resistant and corner-case bugs in high-risk silicon design or IP blocks. Our formal verification service enables you to: 1) Reach your silicon design verification goals faster 2) Uncover hard to find functional bugs in your design 3) Require less RTL simulation time 4) Stay within your budget and tape-out schedule 5) Avoid re-spins and improve designer productivity We functionally verify your RTL with formal techniques and iteratively communicate bugs we find. You get short feedback cycles, reduce your time spent on RTL verification and higher-quality designs. What makes us special? We work with an innovative formal verification methodology, resulting in an easy to use, high quality formal Verification IP. Instead of writing SVA properties by hand we established a property generation flow. During a verification service project, we build a propriatary model that enables us to generate VIP. The VIP can later be used in simulation and/or formal verification of your choice.