Edin Zecic

Edin Zecic is a Project Engineer at CSL since December 2022, responsible for the construction, commissioning, and qualification of Project Banksia within the CSL Seqirus FCC Process Facility. Previously, Edin worked as an Electrical and Instrumentation Engineer at Lycopodium from July 2021, generating various electrical schematics and contributing to diverse projects across multiple industries, including mining and pharmaceuticals. Edin's prior experience includes a role as a Power Quality Engineer at Quality Energy, focusing on a Medium Voltage Power Factor Correction Prototype, and serving as an Electronics Engineer for RMIT Electric Racing. Edin holds a Bachelor of Engineering in Electrical and Electronics Engineering from RMIT University, completed in 2020.