Devansh Rajoria

Devansh Rajoria is an experienced engineering professional currently serving as a Senior Design Engineer at M31 Technology since January 2024. Previously, Devansh worked as a Memory Design Engineer subcontractor at Broadcom and served at Zia Semiconductor Pvt Ltd as Design Engineer II, where contributions included the development of an SPHD SRAM Compiler and various characterization tasks. Devansh also has experience as a Memory Design Engineer subcontractor at STMicroelectronics, focusing on Zero Power SRAM projects and analysis of bitcell performance. Earlier professional roles include application engineering at Synopsys Inc and an internship in RTL design at 3ST Technologies. Devansh holds a Bachelor of Technology degree in Electrical, Electronics and Communications Engineering from Guru Gobind Singh Indraprastha University, completed in 2019.