Amit Wangoo is a seasoned Staff DFT Engineer at Marvell Semiconductor since May 2019, with extensive experience in Design for Test (DFT) spanning over two decades. Previous roles include DFT Consultant positions at Qualcomm and Broadcom Limited, where Amit contributed to scan insertion, production pattern generation, and silicon debug for advanced 10nm and 7nm server chips. At LSI, Amit held the role of Senior DFT Engineer, focusing on block level test insertion and memory BIST for 40nm and 28nm multi-core processors. Amit began a career in DFT at ST Microelectronics as Design Engineer-I and holds a degree from the National Institute of Technology, Tiruchirappalli.
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